Fast Run-Time Fault Location in Dependable FPGAs

Run-time fault location in Field-Programmable Gate Arrays (FPGAs) is important because the resulting diagnostic information is used to reconfigure the FPGA for tolerating permanent faults. In order to minimize the system downtime and increase availability, a fault location technique with very short diagnostic latency is desired. In this paper, we present a fast approach for run-time FPGA fault location that can be used for highavailability reconfigurable systems. By integrating FPGA fault tolerance and Concurrent Error Detection (CED) techniques, our approach can achieve significant availability improvement by minimizing the number of reconfigurations required for FPGA fault location and recovery. The area overhead of our approach is studied and illustrated using applications implemented in FPGAs.